Interactive Visualiser for Dataflow Circuits

Processor Architecture Laboratory – EPFL

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Developed an interactive visualizer implemented in C++ using the Godot framework, allowing users to visualize VHDL circuits. This tool provides developers with an intuitive solution for circuit exploration and debugging. Through graphical representation of the circuit's dynamic behavior, developers can precisely locate errors and understand the execution flow. This project was a bachelor project in collaboration with the Processors Architecture Lab at EPFL.